Verification of Generated HDL Filter Code

Verification of Generated HDL Filter Code

In the final stage, the HDL Filter Code generated is verified so that it is compiler-friendly. Verification of the code facilitates transferring it from the simulation stage to the process synthesis stage. Verification also helps in documenting the working history of the filter structure used, especially if it is a part of an ongoing project.

  • Integration With Third-Party EDA Tools
    • Script Generation Using CLI Properties
    • Script Generation with the EDA Tool Scripts
  • Test Bench Type
  • Test Bench Stimuli
  • Test Bench
  • Resets
  • Postfix for Reference Signal Names
  • Initial Value for Test Bench Inputs
  • Hold Time for Data Input Signals
  • Error Margin for Optimized Filter Code
  • Cosimulation of HDL Code with HDL Simulators
  • Clock